wafer.space Community - WSBB PCB panel designs post-run1

Thought I'd start a thread here - not a fire but we are expecting to want to update the breakout PCB panels for run 2 onwards, based on feedback from the COB supplier(s) Examples of current suggestions have been for slighlty different rails between panels and different qty of rows and columns. I expect that we can confirm any changes by the end of this month or early October, then be ready to order boards mid October. CC @Andrew Wingate and @RebelMike and @Tim 'mithro' Ansell

3:25 p.m.

so TLDR: no action for now, but expect a request for some board/panel revs early Oct and hopefully some time for doing the updates in first couple of weeks of Oct

3:25 p.m.

I'll share further updates here as and when makes sense

Note there's this issue on the CoB repo with some potential changes for discussion: https://github.com/wafer-space/chip-on-board-wire-bonded-pcbs/issues/11

RUN-2 Change Requests · Issue #11 · wafer-space/chip-on-board-wir...

There are a number of changes we may or may not be making for the run-2 versions. Current List: All boards 4 layers Location of the pin1 fiducial Globtop bubble fixes No vias/holes/etc. under globt...

I think this is less about the layout of the CoB board themselves and more about how they are panalized? @stuart - Is that correct?

Tim 'mithro' Ansell

I think this is less about the layout of the CoB board themselves and more about how they are panalized? @stuart - Is that correct?

Yes that's correct, although I wouldn't rule out small tweaks like soldermask between the die and bond pads, area for serial number and similar

7:46 a.m.

Afair one of the die boards still has soldermask between the die and pads for example. I'll ensure we get feedback from the new bonding places so we have a spec to work from